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l q qprox? qt60168, qt60248 16, 24 k ey qm atrix ? ic s applications y automotive panels y machine tools y atm machines y touch-screens y appliance controls y outdoor keypads y security keypanels y industrial keyboards these digital charge-transfer (?qt?) qmatrix? ics are designed to detect human touch on up to 16 or 24 keys when used with a scanned, passive x-y matrix. they will project touch keys through almost any dielectric, e.g. glass, plastic, stone, ceramic, a nd even wood, up to thicknesses of 5 cm or more. the touch areas are defined as simple 2-part interdigitated electrodes of conductive m aterial, like copper or screened silver or carbon deposited on the rear of a control panel. key sizes, shapes and placement are almost e ntirely arbitrary; sizes and shapes of keys can be mixed within a single panel of keys and can vary by a factor of 20:1 in surface area . the sensitivity of each key can be set individually via simple functions over the serial port by a host microcontroller. key setups are stored in an onboard eeprom and do not need to be reloaded with each powerup. these devices are designed specifically for appliances, electronic kiosks, security panels, portable instruments, machine tools , or similar products that are subject to environmental influences or even vandalism. they permit the construction of 100% sealed, watertight control panels that are immune to humidity, temperature, dirt accumulation, or the physical deterioration of the pan el surface from abrasion, chemicals, or abuse. to this end they contain quantum-pioneered adaptive auto self-calibration, drift compensati on, and digital filtering algorithms that make the sensing function robust and survivable. these devices feature continuous fmea self-test and reporting diagnostics, to allow their use in critical consumer appliance applications, for example ovens and cooktops. common pcb materials or flex circuits can be used as the circuit substrate; the overlying panel can be made of any non-conducti ng material. external circuitry consists of only a few passive parts. control and data transfer is via an spi port. these devices makes use of an important new variant of charge-transfer sensing, transverse charge-transfer, in a matrix format that minimizes the number of required scan lines. unlike older methods, it does not require one ic per key. l q copyright ? 2004 qrg ltd qt60248-as r4.02/0405 z second generation charge-transfer qmatrix technology z keys individually adjustable for sensitivity, response time, and many other critical parameters z panel thicknesses to 50mm through any dielectric z 16 and 24 touch key versions z 100% autocal for life - no adjustments required z spi slave interface z adjacent key suppression feature z synchronous noise suppression feature z spread-spectrum modulation - high noise immunity z mix and match key sizes & shapes in one panel z low overhead communications protocol z fmea compliant design features z negligible external component count z extremely low cost per key z +3 to +5v single supply operation z 32-pin lead-free tqfp package x2 x1 x0 /rst y2a y1a y0a y2b x7 vref s _ sync smp drdy / ss mosi miso x3 x4 vss vdd vss vdd x5 x6 sck vdd sync vdd vss n/c y0b y1b 1 2 3 4 5 6 7 817 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 9 10 11 16 15 14 13 12 qt60248 qt60168 tqfp-32 yes qt60248-asg 24 -40 0 c to +105 0 c yes qt60168-asg 16 -40 0 c to +105 0 c lead-free part number # keys t a available options
13 4.8 report error flags for all keys - 0x0b .............. 13 table 4.1 bits for key reporting and numbering ............ 13 4.7 report detections for all keys - 0x07 .............. 13 4.6 report 1st key - 0x06 ...................... 12 4.5 general status - 0x05 ...................... 12 4.4 force reset - 0x04 ....................... 12 4.3 cal all - 0x03 .......................... 12 4.2 enter setups mode - 0x01 .................... 11 4.1 null command - 0x00 ...................... 11 4 control commands ....................... 11 3.3 command error handling .................... 10 3.2 spi communications ...................... 10 3.1 drdy pin ............................ 10 3 serial communications ..................... 9 figure 2.7 wiring diagram ...................... 8 table 2.2 - pin listing ....................... 8 2.17 wiring ............................. 7 2.16 fmea tests .......................... 7 2.15 detection integrators ...................... 7 2.14 spread spectrum acquisitions ................. 6 2.13 reset input .......................... 6 table 2-1 basic timings ...................... 6 2.12 startup / calibration times ................... 6 2.11 power supply considerations ................. 6 2.10.2 pcb cleanliness ....................... 6 2.10.1 led traces and other switching signals ............ 6 2.10 pcb layout, construction ................... 5 2.9 key design ........................... 5 2.8 matrix series resistors ..................... 4 2.7 signal levels .......................... 4 2.6 sample resistors ........................ 4 2.5 sample capacitors; saturation ................. 4 2.4 oscillator ............................ 3 2.3 response time ......................... 3 2.2 disabling keys; burst paring ................... 3 2.1 matrix scan sequence ...................... 3 2 hardware & functional ..................... 3 1.2 enabling / disabling keys .................... 3 1.1 part differences ......................... 3 1 overview .............................. 27 7.3 pcb layout ........................... 27 7.2 1-sided key layout ....................... 26 7.1 8-bit crc algorithm ....................... 26 7 appendix ............................. 25 6.6 marking ............................. 24 6.5 mechanical dimensions ..................... 24 6.4 timing specifications ...................... 24 6.3 dc specifications ........................ 24 6.2 recommended operating conditions ............... 24 6.1 absolute maximum electrical specifications ........... 24 6 specifications .......................... 23 table 5.3 setups block summary .................. 22 table 5.2 key mapping ....................... 22 table 5.1 setups block ....................... 21 5.13 host crc - hcrc ....................... 21 5.12 lower signal limit - lsl .................... 20 5.11 burst spacing - bs ....................... 20 5.10 mains sync - msync ..................... 20 5.9 oscilloscope sync - ssync ................... 20 5.8 adjacent key suppression - aks ................ 20 5.7 burst length - bl ........................ 19 5.6 positive recalibration delay - prd ............... 19 5.5 negative recal delay - nrd ................... 19 5.4 detect integrators - ndil, fdil ................. 18 5.3 drift compensation - ndrift, pdrift ............. 18 5.2 positive threshold - pthr ................... 18 5.1 negative threshold - nthr ................... 18 5 setups ............................... 16 table 4.2 command summary .................... 14 4.18 command sequencing ..................... 14 4.17 cal key ?k? - 0xck ........................ 14 4.16 status for key ?k? - 0x8k .................... 14 4.15 data set for one key - 0x4k .................. 13 4.14 internal code - 0x12 ...................... 13 4.13 internal code - 0x10 ...................... 13 4.12 return last command - 0x0f .................. 13 4.11 eeprom crc - 0x0e ...................... 13 4.10 dump setups block - 0x0d ................... 13 4.9 report fmea status - 0x0c ................... l q 2 qt60248-as r4.02/0405 contents
1 overvie w qmatrix devices are digital burst mode charge-transfer (qt) sensors designed specifically for matrix geometry touch controls; they include all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions. only a few external parts are required for operation. the entire circuit can be built within a few square centimeters of single-sided pcb area. cem-1 and fr1 punched, single-sided materials can be used for possible lowest cost. the pcb?s rear can be mounted flush on the back of a glass or plastic panel using a conventional adhesive, such as 3m vhb 2-sided adhesive acrylic film. qmatrix parts employ transverse charge-transfer ('qt') sensing, a technology that senses changes in electrical charge forced across an electrode by a pulse edge (figure 1-1). qmatrix devices allow for a wide range of key sizes and shapes to be mixed together in a single touch panel. the devices use an spi interface to allow key data to be extracted and to permit individual key parameter setup. the interface protocol uses simple single byte commands and responds with single byte responses in most cases. the command structure is designed to minimize the amount of data traffic while maximizing the amount of information conveyed. in addition to normal operating and setup functions the device can also report back actual signal strengths and error codes. qmbtn software for the pc can be used to program the operation of the ic as well as read back key status and signal levels in real time. the qt60168 and qt60248 are electrically identical with the exception of the number of keys which may be sensed. 1.1 part differences versions of the device are capable of a maximum of 16 or 24 keys (qt60168, qt60248 respectively). these devices are identical in all respects, except that each is capable of only the number of keys specified. these keys can be located anywhere within the electrical grid of 8 x and 3 y scan lines. unused keys are always pared from the burst sequence in order to optimize speed. similarly, in a given part a lesser number of enabled keys will cause any unused acquisition burst timeslots to be pared from the sampling sequence to optimize acquire speed. thus, if only 14 keys are actually enabled, only 14 timeslots are used for scanning. 1.2 enabling / disabling keys the ndil parameter is used to enable and disable keys in the matrix. setting ndil = 0 for a key disables it (section 5.4). at no time can the number of enabled keys exceed the maximum specified for the device in the case of the qt60168. on the qt60168, only the first 2 y lines (y0, y1) are operational by default. on the qt60168, to use keys located on line y2, one or more of the pre-enabled keys must be disabled simultaneously while enabling the desired new keys. this can be done in one setups block load operation. 2 hardware & functional 2.1 matrix scan sequence the circuit operates by scanning each key sequentially, key by key. key scanning begins with location x=0 / y=0 (key #0). x axis keys are known as rows while y axis keys are referred to as columns . keys are scanned sequentially by row, for example the sequence x0y0 x1y0 .... x7y0, x0y1, x1y1... etc. keys are also numbered from 0..24. key 0 is located at x0y0. a table of key numbering is located on page 22. each key is sampled in a burst of acquisition pulses whose length is determined by the setups parameter bl (page 20), which can be set on a per-key basis. a burst is completed entirely before the next key is sampled; at the end of each burst the resulting signal is converted to digital form and processed. the burst length directly impacts key gain; each key can have a unique burst length in order to allow tailoring of key sensitivity on a key by key basis. 2.2 disabling keys; burst paring keys that are disabled by setting ndil =0 (section 5.4, page 19) have their bursts pared from the scan sequence to save time. this has the consequence of affecting the scan rate of the entire matrix as well as the time required for initial matrix calibration. reducing the number of enabled keys also reduces the time required to calibrate an individual key once the matrix is initially calibrated after power-up or reset, since the total cycle time is proportional to the number of enabled keys. keys that are disabled report as follows: signal = 0 reference = 0 low-signal error flag (provided lsl >0) calibrating flag for key set only just after device reset or after a cal command, for one scan cycle only failed calibration error for key always set detect flag for key never set see also section 4.16 notes. 2.3 response time the response time of the device depends on the scan rate of the keys (section 5.11), the number of keys enabled (section 5.4), the detect integrator settings (section 5.4), the serial polling rate by the host microcontroller, and the time required to do fmea tests at the end of each scan (~5ms). l q 3 qt60248-as r4.02/0405 figure 1-1 field flow between x and y elements overlying panel x element y element
for example: nke = number of keys enabled = 20 fdil = fast detect integrator limit = 5 bs = burst spacing = 0.5ms fmea = fmea test time = 5ms ndil = norm detect integrator limit = 2 hpr = host polling rate = 10ms the worst case response time is computed as: tr = ((((nke + fdil) * bs) + fmea) * ndil) + hpr for the above example values: tr = ((((20 + 5) * 0.5ms) + 5ms) * 2) + 10ms = 45ms 2.4 oscillator the oscillator is internal to the device. there is no facility for external clocking. 2.5 sample capacitors; saturation the charge sampler capacitors on the y pins should be the values shown. they should be x7r or np0 ceramics or pps film. the value of these capacitors is not critical but 4.7nf is recommended for most cases. cs voltage saturation is shown in figure 2-1. this nonlinearity is caused by excessively negative voltage on cs inducing conduction in the pin protection diodes. this badly saturated signal destroys key gain and introduces a strong thermal coefficient which can cause 'phantom' detection. the cause of this is usually from the burst length being too long, the cs value being too small, or the x-y coupling being too large. solutions include loosening up the interdigitation of key structures, separating x and y lines on the pcb more, increasing cs, and decreasing the burst length. increasing cs will make the part slower; decreasing burst length will make it less sensitive. a better pcb layout and a looser key structure (up to a point) have no negative effects. cs voltages should be observed on an oscilloscope with the matrix layer bonded to the panel material; if the rs side of any cs ramps more negative than -0.25 volts during any burst (not counting overshoot spikes which are probe artifacts), there is a potential saturation problem. figure 2-2 shows a defective waveform similar to that of 2-1, but in this case the distortion is caused by excessive stray capacitance coupling from the y line to ac ground, for example from running too near and too far alongside a ground trace, ground plane, or other traces. the excess coupling causes the charge-transfer effect to dissipate a significant portion of the received charge from a key into the stray capacitance. this phenomenon is more subtle; it can be best detected by increasing bl to a high count and watching what the waveform does as it descends towards and below -0.25v. the waveform will appear deceptively straight, but it will slowly start to flatten even before the -0.25v level is reached. a correct waveform is shown in figure 2-3. note that the bottom edge of the bottom trace is substantially straight (ignoring the downward spikes). unlike other qt circuits, the cs capacitor values on qt60xx8 devices have no effect on conversion gain. however they do affect conversion time. unused y lines should be left open. 2.6 sample resistors there are 3 sample resistors (rs) used to perform single-slope adc conversion of the acquired charge on each cs capacitor. these resistors directly control acquisition gain: larger values of rs will proportionately increase signal gain. values of rs can range from 380k ohms to 1m ohms. 470k ohms is a reasonable value for most purposes. unused y lines do not require an rs resistor. 2.7 signal levels quantum?s qmbtn? software makes it is easy to observe the absolute level of signal received by the sensor on each key. the signal values should normally be in the range from 250 to 750 counts with properly designed key shapes and values of rs. however, long adjacent runs of x and y lines can also artificially boost the signal values, and induce signal saturation: this is to be avoided. the x-to-y coupling should come mostly from intra-key electrode coupling, not from stray x-to-y trace coupling. qmbtn software is available free of charge on quantum?s website. the signal swing from the smallest finger touch should preferably exceed 10 counts, with 15 being a reasonable target. the signal threshold setting (nthr) should be set to a value guaranteed to be less than the signal swing caused by the smallest touch. l q 4 qt60248-as r4.02/0405 figure 2-1 vcs - non-linear during burst (burst too long, or cs too small, or x-y capacitance too large) figure 2-2 vcs - poor gain, non-linear during burst (excess capacitance from y line to gnd) figure 2-3 vcs - correct
increasing the burst length (bl) parameter will increase the signal strengths as will increasing the sampling resistor (rs) values. 2.8 matrix series resistors the x and y matrix scan lines should use series resistors (referred to as rx and ry respectively) for improved emi performance. x drive lines require them in most cases to reduce edge rates and thus reduce rf emissions. typical values range from 1k to 20k ohms. y lines need them to reduce emc susceptibility problems and in some extreme cases, esd. typical y values range around 1k ohms. y resistors act to reduce noise susceptibility problems by forming a natural low-pass filter with the cs capacitors. it is essential that the rx and ry resistors and cs capacitors be placed very close to the chip. placing these parts more than a few millimeters away opens the circuit up for high frequency interference problems (above 20mhz) as the trace lengths between the components and the chip start to act as rf antennae. the upper limits of rx and ry are reached when the signal level and hence key sensitivity are clearly reduced. the limits of rx and ry will depending on key geometry and stray capacitance, and thus an oscilloscope is required to determine optimum values of both. the upper limit of rx can vary depending on key geometry and stray capacitance, and some experimentation and an oscilloscope are required to determine optimum values. dwell time is the duration in which charge coupled from x to y is captured. increasing rx values will cause the leading edge of the x pulses to increasingly roll off, causing the loss of captured charge (and hence loss of signal strength) from the keys (figure 2-4). the dwell time of these parts is fixed at 375ns. if the x pulses have not settled within 375ns, key gain will be reduced; if this happens, either the stray capacitance on the x line(s) should be reduced (by a layout change, for example by reducing x line exposure to nearby ground planes or traces), or, the rx resistor needs to be reduced in value (or a combination of both approaches). one way to determine x line settling time is to monitor the fields using a patch of metal foil or a small coin over the key (figure 2-5). only one key along a particular x line needs to be observed, as each of the keys along that x line will be identical. the 250ns dwell time should be exceed the observed 95% settling of the x-pulse by 25% or more. in almost all case, ry should be set equal to rx, which will ensure that the charge on the y line is fully captured into the cs capacitor. 2.9 key design circuits can be constructed out of a variety of materials including flex circuits, fr4, and even inexpensive single-sided cem-1. the actual internal pattern style is not as important as is the need to achieve regular x and y widths and spacings of sufficient size to cover the desired graphical key area or a little bit more; ~3mm oversize is acceptable in most cases, since the key?s electric fields drop off near the edges anyway. the overall key size can range from 10mm x 10mm up to 100mm x 100mm but these are not hard limits. the keys can be any shape including round, rectangular, square, etc. the internal pattern l q 5 qt60248-as r4.02/0405 figure 2-4 x-drive pulse roll-off and dwell time figure 2-5 probing x-drive waveforms with a coin x drive lost charge due to inadequate settling before end of dwell time y gate dwell time figure 2-6 recommended key structure ?t? should ideally be similar to the complete thickness the fields need to penetrate to the touch surface. smaller dimensions will also work but will give less signal strength. if in doubt, make the pattern coarser.
can be as simple as a single bar of y within a solid perimeter of x, or (preferably) interdigitated as shown in figure 2-6. for better surface moisture suppression, the outer perimeter of x should be as wide as possible, and there should be no ground planes near the keys. the variable ?t? in this drawing represents the total thickness of all materials that the keys must penetrate. see figure 2-6 and page 27 for examples of key layouts. see section 2.16 for guidance about potential fmea problems with small key shapes. 2.10 pcb layout, construction it is best to place the chip near the touch keys on the same pcb so as to reduce x and y trace lengths, thereby reducing the chances for emc problems. long conn ection traces act as rf antennae. the y (receive) lines are much more susceptible to noise pickup than the x (drive) lines. even more importantly, all signal related discrete parts (r?s and c?s) should be very close to the body of the chip. wiring between the chip and the various r?s and c?s should be as short and direct as possible to suppress noise pickup. ground planes and traces should not be used around the keys and the y lines from the keys. ground areas, traces, and other adjacent signal conductors that act as ac ground (such as vdd and led drive lines etc) will absorb the received key signals and reduce signal-to-noise ratio (snr) and thus will be counterproductive. ground planes around keys will also make water film effects worse. ground planes, if used, should be placed under or around the qt chip itself and the associated r?s and c?s in the circuit, under or around the power supply, and back to a connector, but nowhere else. see page 27 for an example of a 1-sided pcb layout. 2.10.1 led traces and other switching signals digital switching signals near the y lines will induce transients into the acquired signals, deteriorating the snr perfomance of the device. such signals should be routed away from the y lines, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). led terminals which are multiplexed or switched into a floating state and which are within or physically very near a key structure (even if on another nearby pcb) should be bypassed to either vss or vdd with at least a 10nf capacitor of any type, to suppress capacitive coupling effects which can induce false signal shifts. led terminals which are constantly connected to vss or vdd do not need further bypassing. 2.10.2 pcb cleanliness all capacitive sensors should be treated as highly sensitive circuits which can be influenced by stray conductive leakage paths. qt devices have a basic resolution in the femtofarad range; in this region, there is no such thing as ?no clean flux?. flux absorbs moisture and becomes conductive between solder joints, causing signal drift and resultant false detections or transient losses of sensitivity or instability. conformal coatings will trap in existing amounts of moisture which will then become highly temperature sensitive. the designer should specify ultrasonic cleaning as part of the manufacturing process, and in cases where a high level of humidity is anticipated, the use of conformal coatings after cleaning to keep out moisture. 2.11 power supply considerations as these devices use the power supply itself as an analog reference, the power should be very clean and come from a separate regulator. a standard inexpensive ldo type regulator should be used that is not also used to power other loads such as leds, relays, or other high current devices. load shifts on the output of the ldo can cause vdd to fluctuate enough to cause false detection or sensitivity shifts. a single ceramic 0.1uf bypass capacitor should be placed very close to supply pins 3, 4, 5 and 6 of the ic. pins 18, 20, and 21 do not require bypassing. vdd can range from +3 to +5 nominal. the device enters reset below 2.8v via an internal lvd circuit. see section 2.13. 2.12 startup / calibration times the devices require initialization times as follows: normal cold start to ability to communicate: 4ms - normal initialization from any type of reset 22ms - initialization from reset where the setups were previously modified. calibration time per key vs. burst spacings for 16 and 24 enabled keys: 1,040 728 3.00 959 673 2.75 878 618 2.50 797 563 2.25 715 507 2.00 634 452 1.75 553 397 1.50 472 342 1.25 390 286 1.00 309 231 0.75 228 176 0.50 cal time, ms, 24 keys cal time, ms, 16 keys burst spacing, ms table 2-1 basic timings to the above, add the initialization time from above (4ms or 22ms) to get the total elapsed time from reset, to the ability to report key detections over the serial interface. disabled keys are subtracted from the burst sequence and thus the cal time is shortened. the scan time should be measured on an oscilloscope. keys that cannot calibrate for some reason require 5 full cal cycles before they report as errors. the device can report back during the calibration interval that the key(s) affected are still in calibration via status function bits. errors can be observed after a cal cycle using the 0x8k command (see section 4.16). 2.13 reset input the /rst pin can be used to reset the device to simulate a power down cycle, in order to bring the part up into a known l q 6 qt60248-as r4.02/0405
state should communications with the part be lost. the pin is active low, and a low pulse lasting at least 10s must be applied to this pin to cause a reset. to provide for proper operation during power transitions the devices have an internal lvd set to 2.7 volts. the reset pin has an internal 30k ~ 80k resistor. a 2.2f capacitor plus a diode to vdd can be connected to this pin as a traditional reset circuit, but this is not required. a force reset command, 0x04 is also provided which generates an equivalent hardware reset. if an external hardware reset is not used, the reset pin may be connected to vdd or left floating. 2.14 spread spectrum acquisitions qt60xx8 devices use spread-spectrum burst modulation. this has the effect of drastically reducing the possibility of emi effects on the sensor keys, while simultaneously spreading rf emissions. this feature is hard-wired into the device and cannot be disabled or modified. spread spectrum is configured as a frequency chirp over a wide range of frequencies for robust operation. 2.15 detection integrators see also section 5.4, page 19. the devices feature a detection integration mechanism, which acts to confirm a detection in a robust fashion. the basic idea is to increment a per-key counter each time the key has crossed its threshold. when this counter reaches a preset limit the key is finally declared to be touched. example: if the limit value is 10, then the device has to detect a threshold crossing 10 times in succession without interruption, before the key is declared to be touched. if on any sample the signal is not seen to cross the threshold level, the counter is cleared and the process has to start over from the beginning. the qt60xx8 uses a two-tier confirmation mechanism having two such counters for each key. these can be thought of as ?inner loop? and ?outer loop? confirmation counters. the ?inner? counter is referred to as the ?fast-di?; this acts to attempt to confirm a detection via rapid successive acquisition bursts, at the expense of delaying the sampling of the next key. each key has its own fast-di counter and limit value; these limits can be changed via the setups block on a per-key basis. the ?outer? counter is referred to as the ?normal-di?; this di counter increments whenever the fast-di counter has reached its limit value. if a fast-di counter failed to reach its terminal count, the corresponding normal-di counter is also reset. the normal-di counter also has a limit value which is settable on a per-key basis. if a normal-di counter reaches its terminal count, the corresponding key is declared to be touched and becomes ?active?. note that the normal-di can only be incremented once per complete keyscan cycle, ie more slowly, whereas the fast-di is incremented ?on the spot? without interruption. the net effect of this mechanism is a multiplication of the inner and outer counters and hence a highly noise-resistance sensing method. if the inner limit is set to 5, and the outer to 3, the net effect is 5x3=15 successive threshold crossings to declare a key as active. 2.16 fmea tests fmea (failure modes and effects analysis) is a tool used to determine critical failure problems in control systems. fmea analysis is being applied increasingly to a wide variety of applications including domestic appliances. to survive fmea testing the control board must survive any single problem in a way that the overall product can either continue to operate in a safe way, or shut down. the most common fmea requirements regard opens and shorts analysis of adjacent pins on components and connectors. however other criteria must usually be taken into account, for example complete device failure, and the use of redundant signaling paths. qt60xx8 devices incorporate special self-test features which allow products to pass such fmea tests easily. these tests are performed during a dummy timeslot after the last enabled key. the fmea testing is done on all enabled keys in the matrix, and results are reported via the serial interface through a dedicated status command (page 13). disabled keys are not tested. the existence of an error is also reported in normal key reporting commands such as report 1st key, page 13. all fmea tests are repeated every second or faster during normal run operation. sometimes, fmea errors can occur intermittently, for example due to momentary power fluctuations. it is advisable to confirm a true fmea fault condition by making sure the error flags persist for a several seconds. since the devices only communicate in slave mode, the host can determine immediately if the qt has suffered a catastrophic failure. the fmea tests performed are: ? x drive line shorts to vdd and vss ? x drive line shorts to other pins ? x drive signal deviation ? y line shorts to vdd and vss ? y line shorts to other pins ? x to y line shorts ? cs capacitor checks including shorts and opens ? vref test ? key gain test other tests incorporated into the devices include: ? a test for signal levels against a preset min value (lsl setup, see page 21). if any signal level falls below this level, an error flag is generated. ? crc communications checks on all critical command and data transmissions. ? ?last-command? command to verify that an instruction was properly received. some very small key designs have very low x-y coupling. in these cases, the amount of signal will be very small, and the key gain will be low. as a result, small keys can fail the lsl test (page 21) or the fmea key gain test (above). in such cases, the burst length of the key should be increased so that the key gain increases. failing that, a small ceramic capacitor, for example 3pf, can be added between the x and y lines serving the key to artificially boost signal strength. for those applications requiring it, quantum can supply sample fmea test data on special request. l q 7 qt60248-as r4.02/0405
2.17 wiring table 2.2 - pin listing leave open x2 matrix drive line o x2 32 leave open x1 matrix drive line o x1 31 leave open x0 matrix drive line o x0 30 leave open or vdd reset low; has internal 30k ~ 80k pull-up i /rst 29 y2a line connection i y2a 28 leave open y1a line connection i y1a 27 y0a line connection i y0a 26 leave open y2b line connection i y2b 25 y1b line connection i y1b 24 leave open y0b line connection i y0b 23 leave open not used n/a nc 22 - supply ground p vss 21 - power, +3 ~ +5v p vdd 20 vdd mains sync input i sync 19 - power, +3 ~ +5v p vdd 18 - spi clock input i sck 17 - spi data output o miso 16 - spi data input i mosi 15 - spi slave select; has internal 20k ~ 50k pull-up i /ss 14 - 1= comms ready; has internal 20k ~ 50k pull-up o drdy 13 - sample drive output o smp 12 leave open scope sync: synchronization test signal output o s_sync 11 - 0.05v nominal +/-10% via external divider i vref 10 leave open x7 matrix drive line o x7 9 leave open x6 matrix drive line o x6 8 leave open x5 matrix drive line o x5 7 - power, +3 ~ +5v p vdd 6 - supply ground p vss 5 - power, +3 ~ +5v p vdd 4 - supply ground p vss 3 leave open x4 matrix drive line o x4 2 leave open x3 matrix drive line o x3 1 if unused, connect to.. comments i/o function pin l q 8 qt60248-as r4.02/0405
figure 2.7 wiring diagram see table 2.2 for further connection information. l q 9 qt60248-as r4.02/0405 + matrix y scan in matrix x drive miso mosi drdy note 1 ss sclk + 10k 100 rs2 470k rs0 470k 1k rx2 1k rx6 1k ry1 1k ry2 1k ry0 1k rx0 1k rx4 vunreg +3 to +5v vreg vdd qt60248 qt60168 100nf line sync scope sync note 2 note 2 vdd spi 4.7uf 4.7uf rs1 470k note 1: wire 100nf bypass cap very close to pins 3, 4, 5, 6 note 2: leave y2a, y2b unconnected for qt60168 cs1 4.7nf 1k rx1 1k rx3 1k rx7 cs2 4.7nf 4.7nf cs0 1k rx5
3 serial communications these devices use spi communications, in slave mode. the host device always initiates communications sequences; the qt is incapable of chattering data back to the host. this is intentional for fmea purposes so that the host always has total control over the communications with the qt60xx8. in spi mode the device is a slave, so that even return data following a command is controlled by the host. a command from the host always ends in a response of some kind from the qt. some transmission types from the host or the qt employ a crc check byte to provide for robust communications. a drdy line is provided that handshakes transmissions. generally this is needed by the host from the qt to ensure that transmissions are not sent when the qt is busy or has not yet processed a prior command. initiating or resetting communications: after a reset, or, should communications be lost due to noise or out-of-sequence reception, the host should send a 0x0f (return last command) command repeatedly until the compliment of 0x0f, i.e. 0xf0, is received back. then, the host can resume normal run mode communications from a clean start. poll rate: the typical poll rate in normal ?run? operation should be no faster than once per 10ms; 25ms is more than fast enough to extract status data using the 0x06 command (report first key: see page 13) in most situations. streaming multi-byte response commands like the 0x0d command (dump setups: see page 13) or multi-byte response commands like 0x07 can and should pace at the maximum possible rate. run poll sequence: in normal run mode the host should limit traffic with a minimalist control structure (see also section 4.18). the host should just send a 0x06 command until something requires a deeper state inspection. if there is more than one key in detect, the host should use 0x07 to find which additional keys are in detect. if there is an error, the host should ascertain the error type based on commands 0x0b and 0x0c and take appropriate action. issuing a 0x07 command all the time is wasteful of bandwidth, requires more host processor time, and actually conveys less information (no error flags are sent via a 0x07 command). 3.1 drdy pin drdy is an open-drain output with an internal 20k ~ 50k pullup resistor. serial communications pacing is controlled by this pin. the host is permitted to send data only when drdy is high. after a byte is received drdy will always go low even if only for a few microseconds; during this period the host should not send data. therefore, after each byte transmission the host should first check that drdy is high again. if the host desires to send a byte to the qt it should behave as follows: 1. if drdy is low, wait 2. if drdy is high: send a command to qt 3. wait at least 40s (time s5 in figure 3-3: drdy is guaranteed to go low before this 40s expires) 4. wait until drdy is high (it may already be high again) 5. send next command or a null byte 0x00 to qt the time it takes for drdy to go high again after a command depends on the command. following is a list of commands and the time required to process them and then raise drdy: 0x0e eeprom crc [ 25ms 0x01 load setups [ 25ms all other commands: [ 2ms between bytes; [ 40s after crc byte is sent other drdy specs: min time drdy is low: 1s min time drdy is low after reset: 1ms 3.2 spi communications spi communications operates in slave mode only, and obeys drdy control signaling. the clocking is as follows: clock idle: high clock shift out edge: falling clock data in edge: rising max clock rate: 1.5mhz spi mode requires 5 signals to operate: mosi - master out / slave in data pin; used as an input for data from the host (master). this pin should be connected to the mosi (do) pin of the host device. miso - master in / slave out data pin; used as an output for data to the host. this pin should be connected to the miso l q 10 qt60248-as r4.02/0405 figure 3-2 filtered spi connections mosi miso sck drdy ss qt60 x x 8 circuit ra 1k ra ra ra ra reset 1k host mcu 1k yn xn x drives (1 of 8 shown) y lines (1 of 3 shown) ca ca ca ca ca 1nf sck miso mosi p_in p_out1 p_out2 1nf 2,200 50khz 470pf 2,200 100khz 270pf 1,000 400khz 100pf 680 1.5mhz ca ra spi clock rate recommended values of ra & ca figure 3-1 basic spi connections mosi mosi miso miso sck sck drdy p_out p_in ss host mcu qt60xx8
(di) pin of the host. miso floats when /ss is high to allow multi-drop communications along with other slave parts. sck - spi clock - input only clock from host. the host must shift out data on the falling sck edge; the qt60xx8 clocks data in on the rising edge. the qt60xx8 likewise shifts data out on the falling edge of sck back to the host so that the host can shift the data in on the rising edge. important: sck must idle high; it should never float. /ss - slave select - input only; acts as a framing signal to the sensor from the host. /ss must be low before and during reception of data from the host. it must not go high again until the sck line has returned high; /ss must idle high. this pin includes an internal pull-up resistor of 20k ~ 50k. when /ss is high, miso floats. drdy - data ready - active-high - indicates to the host that the qt is ready to send or receive data. this pin idles high. this pin includes an internal pull-up resistor of 20k ~ 50k. in spi mode this pin is an output only (i.e. open drain with internal pull-up). the miso pin on the qt floats in 3-state mode between bytes when /ss is high. this facilitates multiple devices on one spi bus. null bytes: when the qt responds to a command with one or more response bytes, the host should issue a null commands (0x00) to get the response bytes back. the host should not send new commands until all the responses are accepted back from the qt from the prior command via nulls. new commands attempted during intermediate byte transfers are ignored. spi line noise: in some designs it is necessary to run spi lines over ribbon cable across a lengthy distance on a pcb. this can introduce ringing, ground bounce, and other noise problems which can introduce false spi clocking or false data. simple rc networks and slower data rates as shown in figure 3-2 are helpful to resolve these issues. crc checks have been added to critical commands in order to detect transmission errors to a high level of certainty. 3.3 command error handling if an unrecognized command is received, the device will release drdy high and the communications error flag will be set in the general status byte (see section 4.5). 4 control commands refer to table 4.2, page 16 for further details. the devices feature a set of commands which are used for control and status reporting. the host device has to send the command to the qt60xx8 and await a response. spi mode: while waiting the host should delay for 40s from the end of the command, then start to check if drdy is or goes high. if it is high, then the host master can clock out the resulting byte(s). command timeouts: where a command involves multi-byte transfers in either direction, each byte must be transmitted within 100ms of the prior byte or the command will timeout. no error is reported for this condition; the command simply ceases. word return byte order: where a word or long word is returned (16 or 24 bit number or bit pattern) the low order byte is sent or received first. 4.1 null command - 0x00 used to shift back data from the qt. since the host device is always the master in spi mode, and data is clocked in both directions, the null command is required frequently to act as a placeholder where the desire is to only get data back from the qt, not to send a command. in spi communications, when the qt60xx8 responds to a command with one or more response bytes, the host can issue a new command instead of a null on the last byte shift operation. new commands during intermediate byte shift-out operations are ignored, and null bytes should always be used. l q 11 qt60248-as r4.02/0405 figure 3-3 spi slave-only mode timing s1: m 333ns s2: [ 20ns s3: m 25ns s4: [ 20ns s5: [ 40s s6: m 1s s7: m 333ns s8: m 333ns s9: m 667ns s6 high via pullup-r drdy (from qt) s1 s5 /ss (from host) s3 clk (from host) mosi (data from host) miso 3-state 3-state (data from qt) 0 2 3 6 71 210 4 5 4 50 1 2 3 765 6 7 210 ? ? 43 543 ? 076 ? 7654321 76543210 s7 s9 s8 data shifts out of qt on falling edge data response {optional 2nd command byte} {null byte or next command to get qt response} data shifts in to qt on rising edge {command byte} s4 s2
4.2 enter setups mode - 0x01 this command is used to initiate the setups block transfer from host to qt. the command must be repeated 2x within 100ms or the command will fail; the repeating command must be sequential without any intervening command. after the 2nd 0x01 from the host, the qt will stop scanning keys and reply with the character 0xfe. in spi mode this character must be shifted out by sending a null (0x00) from the host. this command suspends normal sensing starting from the receipt of the second 0x01. a failure of the command will cause a timeout. each byte in the block must arrive at the qt no later than 100ms after the previous one or a timeout will occur. any timeout will cause the device to cancel the block load and go back to normal operation. if no response comes back, the command was not received and the device should preferably be reset from the host by hardware reset just in case there are any other problems. if 0xfe is received by the host, then the host should begin to transmit the block of setups to the qt. drdy handshakes the data. the delay between bytes can be as short as 10s but the host can make it longer than this if required, but no more than 100ms. the last byte the host should send is the crc for the block of data only, ie the command itself should not be folded into the crc. after the block transfer the qt will check the crc and respond with 0x00 if there was an error. regardless, it will program the internal eeprom. if the crc was correct it will reply with a second 0xfe after the eeprom was programmed. at the end of the full block load sequence, the device restarts sensing without recalibration. it is highly recommended that the part be reset after a block load to allow the part to properly initialize itself, clear any setup flags, using the reset command or the reset pin. 4.3 cal all - 0x03 this command must be repeated 2x within 100ms or the command will fail; the repeating command must be sequential without any intervening command. after the 2nd 0x03 from the host, the qt will reply with the character 0xfc. shortly thereafter the device will recalibrate all keys and restart operation. if no 0xfc comes back, the command was not properly received and the device should preferably be reset. the host can monitor the progress of the recalibration by checking the status byte, using command 0x05. a key will show an error flag (via command 0x8k) indicating the key has failed calibration if its signal is too noisy or if its signal is below the low signal threshold. a key is deemed too noisy if, at the end of calibration, the signal is no longer between its computed negative hysteresis level and positive thresholds. 4.4 force reset - 0x04 the command must be repeated 2x within 100ms or the command will fail; the repeating command must be sequential without any intervening command. after the 2nd 0x04, the qt will reply with the character 0xfb just prior to executing the reset operation. the host can monitor the progress of the reset by checking the status byte for recalibration, using command 0x05. the complete reset sequence is as follows: 1. reset command received by qt 2. response byte (0xfb) recovered by host 3. drdy floats high 4. 20ms elapses until device completes reset 5. drdy clamped low 6. 4ms or 22ms elapses - (see section 2.12) 7. drdy floats high again - device reset has completed if the host does not recover the response byte in step 2, the qt device will self-reset within 2 seconds. 4.5 general status - 0x05 this command returns the general status bits. they are as follows: 1= any key in detect 0 1= any key in calibration 1 1= calibration has failed on an enabled key or, an lsl failure 2 1= mains sync error 3 reserved 4 1= fmea failure detected 5 1= communications error 6 reserved 7 description bit notes: bit 7: reserved bit 6: set if a communications failure, such as an unrecognized command. this bit can be reset by sending command 0x0f (?last command command?) repeatedly until a response of 0xf0 is received. bit 5: set if an fmea error was detected during operation. see section 2.16. a further amplification of what the fmea error consisted of is described in section 4.9. bit 4: reserved bit 3: set if there was a mains sync error, for example there was no sync signal detected within the allotted 100ms amount of time. see section 5.10. this condition is not necessarily fatal to operation, however the device will operate very slowly and may suffer from noise problems if the sync feature was required for noise reasons. bit 2: reports either a cal failure (failed in 5 sequential attempts) on any enabled key or, that an enabled key has a very low signal reference value, lower than the user-settable lsl value (section 5.12). disabled keys do not cause this bit 2 error flag to be set even if they generate an error flag in the 0x8k response. bit 1: set if any key is in the process of calibrating. bit 0: set if any key is in detection (touched). a crc byte is appended to the response to the 0x05 command; this crc folds in the command value 0x05 itself initially. l q 12 qt60248-as r4.02/0405
4.6 report 1st key - 0x06 reports the first or only key to be touched, plus indicates if there are yet other keys that are also touched. the return bits are as follows: key bit 0 0 key bit 1 1 key bit 2 2 key bit 3 3 key bit 4 4 unused 5 1= any error condition is present 6 1= more than 1 key is active 7 description bit bits 4..0 encode for the first detected key in range 0..23. if no keys are active, these 5 bits are all 1?s (0x1f, 31 decimal when bits 5, 6, 7 are masked off). disabled keys do not report as active and do not generate an error flag in bit 6, even if they are reporting an error via command 0x8k. if 2 or more keys in detection, bit 7 is set and the host should interrogate the part via the 0x07 command to read out all the key detections. this one command should be the dominant interrogation command in the host interface; further commands can be issued if the response to 0x06 warrants it. a crc byte is appended to the response; this crc folds in the command 0x06 itself initially. 4.7 report detections for all keys - 0x07 returns three bytes which indicate all keys in detection if any, as a bitfield; active keys report as 1?s.. key 0 reports in bit 0 of the first byte returned; key 23 is reported in bit 7 of the last byte returned. see table 4.1 and table 5.2. disabled keys report as inactive (0). a crc byte is appended to the response; this crc folds in the command 0x07 itself initially. table 4.1 bits for key reporting and numbering 16 17 18 19 20 21 22 23 2 8 9 10 11 12 13 14 15 1 0 1 2 3 4 5 6 7 0 byte number returned (y line #) 0 1 2 3 4 5 6 7 bit number (x line #) key # 4.8 report error flags for all keys - 0x0b returns three bytes which show error flags as a bitfield for all keys. key 0 reports in bit 0 of the first byte returned; key 23 is reported in bit 7 of the last byte returned. see table 4.1 and table 5.2. a key that is in calibration also is reported as an error in the response. the error flag is self-cleared once the key successfully exits from calibration. important note: these error bits exclude fmea error flags. a crc byte is appended to the response; this crc folds in the command 0x0b itself initially. 4.9 report fmea status - 0x0c returns one byte which shows the fmea error status of the x and/or y matrix scan lines. if an x line is in error, the corresponding bit (below) is set. if a y line has an fmea error, the entire field is set to ones (0xff). due to the physics of matrix wiring, a fault on any y line will cause faults to be reported on all x lines as well. it is not possible to separate out these faults for reporting purposes. x0 x1 x2 x3 x4 x5 x6 x7 b0 b1 b2 b3 b4 b5 b6 b7 a crc byte is appended to the response; this crc folds in the command 0x0c itself initially. sometimes, fmea errors can occur intermittently, for example due to momentary power fluctuations. it is advisable to confirm a true fmea fault condition by making sure the error flags persist for a several seconds. for more information see section 2.16. 4.10 dump setups block - 0x0d this command causes the device to dump the entire internal setups block back to the host. if the transfer is not paced faster than 100ms per byte the transfer will be aborted and the device will time out. this can happen if the host is also controlling drdy. during the transfer, sensing is halted. sensing is resumed after the command has finished. an 8-bit crc is appended to the response; this crc is the same as the setups table crc. 4.11 eeprom crc - 0x0e this command returns the 8-bit crc byte calculated from the eeprom contents. the crc sent back is the same crc that is appended to the end of the setups block. this command requires substantial amounts of time to process and return a result; it is not recommended to use this command except perhaps on startup or very infrequently. no crc is appended to the response. 4.12 return last command - 0x0f this command returns the last received command character, in 1?s complement (inverted). if the command is repeated twice or more, it will return the inversion of 0x0f, 0xf0. if a prior command was not valid or was corrupted, it will return the bad command as well. this command also will reset the communications error flag (section 4.5). no crc is appended to the response. 4.13 internal code - 0x10 this command returns a 1-byte internal code. a crc byte is appended to the response; this crc folds in the command 0x10 itself initially. 4.14 internal code - 0x12 this command returns an internal code byte of the part for factory diagnostic purposes. a response might take as long as 500ms. no crc is appended to the response. l q 13 qt60248-as r4.02/0405
4.15 data set for one key - 0x4k returns the data set for key k, where k = {0..23} encoded into the low nibble of this command. this command returns 5 bytes, in the sequence: signal (2 bytes) reference (2 bytes) normal detect integrator (1 byte) signal and reference are returned lsbyte first. no crc is appended. keys that are disabled report ?0? for both signal and reference. 4.16 status for key ?k? - 0x8k returns a bitfield for key ?k? where k is from {0..23}. the bitfield indicates as follows: 1= cal on this key failed 5 times 0 1= this key is in cal 1 1= signal ref < lsl (low signal error) 2 1= key is in detect 3 1= key is enabled 4 1= reserved 5 1= reserved 6 1= reserved 7 description bit bit 2 - lsl notes: see page 21. a crc byte is appended to the response; this crc folds in the command 0x8k itself initially. disabled keys: a disabled key never reports as being in detect, but always reports an lsl error (if lsl >0). an lsl error flag generated for this reason is not reflected elsewhere, for example via the 0x05 or 0x06 commands. an lsl error on an enabled key is however reflected in the 0x05 and 0x06 commands. a disabled key also reports back with bit 0 high (failed cal). a cal error flag generated for this reason is not reflected elsewhere, for example via the 0x05 or 0x06 commands. a cal error on an enabled key is however reflected in the 0x05 and 0x06 commands. just after reset or after a cal command (commands 0x03 or 0xck), a disabled key will report back as being in calibration for only one matrix scan cycle, then will report as having failed cal. see also section 2.2. 4.17 cal key ?k? - 0xck this command must be repeated 2x within 100ms or the command will fail; the repeating command must be sequential without any intervening command. this command functions the same as 0x03 cal command except this command only affects one key ?k? where ?k? is from 0 to 23. the chosen key ?k? is recalibrated in its native timeslot; normal running of the part is not interrupted and all other keys operate correctly throughout. this command is for use only during normal operation to try to recover a single key that has failed or is not calibrated correctly. returns the 1?s compliment of 0xck just before the key is recalibrated. 4.18 command sequencing to interface the device with a host, the flow diagram of figure 4-1, page 15, is suggested. the actual settings of the setups block used should normally just be the default settings except where changes are specifically required, such as for sensiti vity, timing, or aks changes. the circles in this drawing are communications interchanges between host and sensor. the rectangles are internal host states or processing events. if any communications exchange fails, either the device will fail to respond within the allotted time, or the response crc will be incorrect, or the response will be out of context (the response is clearly not for the intended command). in these cases the host should just repeat the command. the control flow will spend 99% of its time alternating between the two states within the dashed rectangle. if a key is detected, the control flow will enter ?key detection processing?. stuck key detection processing (0xck) is optional, since the device contains the max on-duration timeout function and can therefore recalibrate the stuck key automatically. however, the host can recalibrate stuck keys with greater flexibility if the recalibration timeouts are set to infinite and the host recalibrates them under specific conditions. error handling takes place whenever an error flag is detected, or the device stops communicating (not shown). the error handling procedure is up to the designer, however normally this would entail shutting down the product if the error is serious enough (for example, a key that will not calibrate, or a fmea class error). an eeprom crc error report is serious, and requires that the host reload the setups table into the device and thereafter issue a reset command or hardware reset. the ?last command? command can be used at any time to clear comms error flags and to resynchronize failed communications, for example due to timing errors etc. l q 14 qt60248-as r4.02/0405
l q 15 qt60248-as r4.02/0405 figure 4-1 suggested communications flow 0x0e setups crc check 0x04 force reset 0x06 report 1st key 0x07 report all detections only 1 key in detect 0xck cal key 'k' ~10ms delay key detection(s) processing no key, no error m m m m 2 keys detected resolvable error 0x0f get 'last command' (clear error) comms error setups crc failed 2x setups crc failed 1x 0x05 get general status calibration fail, or fmea fail, or multiple errors crc is ok power on or hardware reset stuck key detected (optional) 0x0c get fmea status 0x0b get errors for all keys error handling error flag (takes precedence) fmea error calibration error done keys ok note: crc errors or incorrect responses should cause each transmission to retry internal host processes comms with qt 0x0f get 'last command' 0xf0 returned 0xf0 not returned 0x01 load setups block
13 2nd return byte is crc-8 of cmmd + return data yes 0..0xff 2 1 fmea bitfield on x, y lines fmea status 0x0c 13 4th return byte is crc-8 of cmmd + return data yes 0..0xff 3 bytes 4 1 error bit fields error flags for all 0x0b 13 4th return byte is crc-8 of cmmd + return data yes 0..0xff 3 bytes 4 1 sends back all key detect status bits (bitfield) report all keys 0x07 13 bit 7: 1= indicates 2 or more touches if set. bit 6: 1= any of the following conditions prevail: calibrating, key(s) failed cal 5 times, sync fail, comms error, fmea failure. bit 5: unused bits 4..0: indicates key number (0..23) of first key touched; reads 0x1f (31 decimal) if no touch. 2nd return byte is crc-8 of cmmd + return data yes 0..0xff 2 1 get indication of first touched key + others report 1st key 0x06 12 bit 7: reserved bit 6: 1= comms error: unrecognized command received this bit can be reset by the 0x0f cmmd bit 5: 1= fmea failure bit 4: 1= reserved bit 3: 1= line sync failure bit 2: 1= cal failed 5 times on an enabled key, or, an enabled key has a low reference (ref < lsl) bit 1: 1= any key in calibration bit 0: 1= any key is in detect 2nd return byte is crc-8 of cmmd + return data yes 0..0xff 2 1 get general part status. general status 0x05 12 returns 1?s complement of command to acknowledge command prior to reset. if 2 commands not received in 100ms, times out and no response is issued. - 0xfb 1 2 force device to reset. command must be repeated 2x consecutively without any intervening command in 100ms to execute force reset 0x04 12 returns 1?s complement of command to acknowledge cmd once the cal has been initiated. if 2 commands not received in 100ms, times out and no response is issued. - 0xfc 1 2 force device to recalibrate all keys; re-enters run mode afterwards automatically; 0x03 must be repeated 2x consecutively without any intervening command in 100ms to execute cal all 0x03 12 first 0xfe issued when ready to get data, second 0xfe issued when all loaded and burned; else timeout. if 2 commands not received in 100ms, times out and no response is issued. part will timeout if each byte not received within 100ms of previous byte. if crc failure, returns 0x00 instead of 0xfe data block length is 100 + 1 (added +1 byte is crc-8). lsl should be sent low byte first. a crc of 0x00 is also acceptable in which case the crc is not checked. the internal eeprom will be programmed regardless of crc health. - 0xfe + 0xfe or 0xfe + 0x00 (err) 2 2 +100 +1 enter setups, stop sensing; followed by block load of binary setups of length ?nn?. command must be repeated 2x consecutively without any intervening command in 100ms to execute. sensing auto-restarts, however, the device should be reset after the block load to ensure all new setups will take effect. enter setups mode 0x01 11 flushes pending data from qt; one required to extract each response byte. - 0..0xff 1 1 used to get data back in spi mode null command 0x00 page notes crc rtn range # rtnd #/cmd description name hex table 4.2 command summary l q 16 qt60248-as r4.02/0405
14 used in run mode. normal sensing of other keys not affected. cal of ?k? only takes place in the key?s normal timeslot. returns the ones compliment of the cmd char, once the cal is scheduled. - ~0xck 1 2 force calibration of key # k where k= 0..23. command must be repeated 2x consecutively without any intervening command in 100ms to execute cal key ?k? 0xck 14 bits 7..5: reserved bit 4: 1= key is enabled bit 3: 1= key is in detect bit 2: 1= (ref < lsl), even on a disabled key bit 1: 1= key is in calibration bit 0: 1= calibration of this key failed 5 times second return byte is crc of cmmd + return data yes 0..0xff 2 1 get status byte for key ?k? {0..23} status for key ?k? 0x8k 14 diagnostic use only, not to be relied upon (no crc). signal and ref are tx as 2 bytes, lsb first. - 0..0xff each byte 5 1 get signal, ref, norm di for key k {0..23} signal: 2 bytes; ref: 2 bytes; norm di: 1 byte data for 1 key 0x4k 13 returns 1?s compliment of last command even if bad. resets the communications error flag. - 0..0xff 1 1 returns last command received return last cmmd 0x0f 13 crc-8 only on setups array section of eeprom this crc is the same as the crc at the end of setups block load. yes 0..0xff 1 1 get eeprom crc eeprom crc 0x0e 13 100 block data bytes + 1 crc byte returned. yes 0..0xff each byte 100 1 returns setups block area followed by crc. scanning is halted and then auto-restarted after the cmd has completed. dump setups 0x0d page notes crc rtn range # rtnd #/cmd description name hex l q 17 qt60248-as r4.02/0405
5 setups the devices calibrate and process all signals using a number of algorithms specifically designed to provide for high survivability in the face of adverse environmental challenges. they provide a large number of processing options which can be user-selected to implement very flexible, robust keypanel solutions. user-defined setups are employed to alter these algorithms to suit each application. these setups are loaded into the device in a block load over the serial interface. the setups are stored in an onboard eeprom array. after a setups block load, the device should be reset to allow the new setups parameters to take effect. this reset can be either a hardware or software reset. refer to table 5.1, page 22 for a table of all setups. block length issues: the setups block is 100 bytes long to accommodate 24 keys. this can be a burden on smaller host controllers with limited memory. in larger quantities the devices can be procured with the setups block preprogrammed from quantum. if the application only requires a small number of keys (such as 16) then the setups table can be compressed in the host by filling large stretches of the setups area with nulls. many setups employ lookup-table value translation. the setups block summary on page 23 shows all translation values. default values shown are factory defaults. 5.1 negative threshold - nthr the negative threshold value is established relative to a key?s signal reference value. the threshold is used to determine key touch when crossed by a negative-going signal swing after having been filtered by the detection integrator. larger absolute values of threshold desensitize keys since the signal must travel farther in order to cross the threshold level. conversely, lower thresholds make keys more sensitive. as cx and cs drift, the reference point drift-compensates for these changes at a user-settable rate; the threshold level is recomputed whenever the reference point moves, and thus it also is drift compensated. the amount of nthr required depends on the amount of signal swing that occurs when a key is touched. thicker panels or smaller key geometries reduce ?key gain?, ie signal swing from touch, thus requiring smaller nthr values to detect touch. the negative threshold is programmed on a per-key basis using the setup process. see table, page 23. negative hysteresis: nhyst is fixed at 12.5% of the negative threshold value and cannot be altered . typical values : 3 to 8 (7 to 12 counts of threshold; 4 is internally added to nthr to generate the threshold). default value: 6 (10 counts of threshold) 5.2 positive threshold - pthr the positive threshold is used to provide a mechanism for recalibration of the reference point when a key's signal moves abruptly to the positive. this condition is not normal, and usually occurs only after a recalibration when an object is touching the key and is subsequently removed. the desire is normally to recover from these events quickly. positive hysteresis: physt is fixed at 12.5% of the positive threshold value and cannot be altered. positive threshold levels are all fixed at 6 counts of signal and cannot be modified. 5.3 drift compensation - ndrift, pdrift signals can drift because of changes in cx and cs over time and temperature. it is crucial that such drift be compensated, else false detections and sensitivity shifts can occur. drift compensation (figure 5-1) is performed by making the reference level track the raw signal at a slow rate, but only while there is no detection in effect. the rate of adjustment must be performed slowly, otherwise legitimate detections could be ignored. the devices drift compensate using a slew-rate limited change to the reference level; the threshold and hysteresis values are slaved to this reference. when a finger is sensed, the signal falls since the human body acts to absorb charge from the cross-coupling between x and y lines. an isolated, untouched foreign object (a coin, or a water film) will cause the signal to rise very slightly due to an enhancement of coupling. this is contrary to the way most capacitive sensors operate. once a finger is sensed, the drift compensation mechanism ceases since the signal is legitimately detecting an object. drift compensation only works when the signal in question has not crossed the negative threshold level. the drift compensation mechanism can be asymmetric; the drift-compensation can be made to occur in one direction faster than it does in the other simply by changing the ndrift setup parameter. this can be done on a per-key basis. the pdrift parameter is fixed at 0.4 seconds per count of reference drift. specifically, drift compensation should be set to compensate faster for increasing signals than for decreasing signals. decreasing signals should not be compensated quickly, since an approaching finger could be compensated for partially or entirely before even touching the touch pad. l q 18 qt60248-as r4.02/0405 figure 5-1 thresholds and drift compensation threshold signal hysteresis reference output
however, an obstruction over the sense pad, for which the sensor has already made full allowance for, could suddenly be removed leaving the sensor with an artificially suppressed reference level and thus become insensitive to touch. in this latter case, the sensor should compensate for the object's removal by raising the reference level relatively quickly. drift compensation and the detection time-outs work together to provide for robust, adaptive sensing. the time-outs provide abrupt changes in reference calibration depending on the duration of the signal 'event'. ndrift typical values: 9 to 11 (2 to 3.3 seconds per count of drift compensation) ndrift default value: 10 (2.5s / count of drift compensation) pdrift fixed value: 0.4 secs note: this value cannot be altered and does not appear in the setups block. 5.4 detect integrators - ndil, fdil ndil is used to enable or disable keys and to provide signal filtering. to enable a key, its ndil parameter should be non-zero (ie ndil=0 disables a key). see section 2.2. to suppress false detections caused by spurious events like electrical noise, the device incorporates a 'detection integrator' or di counter mechanism that acts to confirm a detection by consensus (all detections in sequence must agree). the di mechanism counts sequential detections of a key that appears to be touched, after each burst for the key. for a key to be declared touched, the di mechanism must count to completion without even one detection failure. the di mechanism uses two counters. the first is the ?fast di? counter fdil. when a key?s signal is first noted to be below the negative threshold, the key enters ?fast burst? mode. in this mode the burst is rapidly repeated for up to the specified limit count of the fast di counter. each key has its own counter and its own specified fast-di limit (fdil), which can range from 1 to 15. when fast-burst is entered the qt device locks onto the key and repeats the acquire burst until the fast-di counter reaches fdil, or, the detection fails beforehand. after this the device resumes normal keyscanning and goes on to the next key. the ?normal di? counter counts the number of times the fast-di counter reached its fdil value. the normal di counter can only increment once per complete scan of all keys. only when the normal di counter reaches ndil does the key become formally ?active?. the net effect of this is that the sensor can rapidly lock onto and confirm a detection with many confirmations, while still scanning other keys. the ratio of ?fast? to ?normal? counts is completely user-settable via the setups process. the total number of required confirmations is equal to fdil times ndil. if fdil = 5 and ndil = 2, the total detection confirmations required is 10, even though the device only scanned through all keys only twice. the di is extremely effective at reducing false detections at the expense of slower reaction times. in some applications a slow reaction time is desirable; the di can be used to intentionally slow down touch response in order to require the user to touch longer to operate the key. if fdil = 1, the device functions conventionally; each channel acquires only once in rotation, and the normal detect integrator counter (ndil) operates to confirm a detection. fast-di is in essence not operational. if fdil m 2, then the fast-di counter also operates in addition to the ndil counter. if signal [ nthr: the fast-di counter is incremented towards fdil due to touch. if signal >nthr then the fast-di counter is cleared due to lack of touch. disabling a key: if ndil =0, the key becomes disabled. keys disabled in this way are pared from the burst sequence in order to improve sampling rates and thus response time. see section 2.2, page 3. ndil typical values : 2, 3 ndil default value: 2 fdil typical values : 4 to 6 fdil default value: 5 5.5 negative recal delay - nrd if an object unintentionally contacts a key resulting in a detection for a prolonged interval it is usually desirable to recalibrate the key in order to restore its function, perhaps after a time delay of some seconds. the negative recal delay timer monitors such detections; if a detection event exceeds the timer's setting, the key will be automatically recalibrated. after a recalibration has taken place, the affected key will once again function normally even if it is still being contacted by the foreign object. this feature is set on a per-key basis using the nrd setup parameter. nrd can be disabled by setting it to zero (infinite timeout) in which case the key will never auto-recalibrate during a continuous detection (but the host could still command it). nrd is set using one byte per key, which can range in value from 0..254. nrd above 0 is expressed in 0.5s increments. thus if nrd =120, the timeout value will actually be 60 seconds. 255 is not a legal number to use. nrd typical values: 20 to 60 (10 to 30 seconds) nrd default value: 20 (10 seconds) nrd range: 0..254 ( , 0.5 .. 127s) 5.6 positive recalibration delay - prd a recalibration occurs automatically if the signal swings more positive than the positive threshold level. this condition can occur if there is positive drift but insufficient positive drift compensation, or, if the reference moved negative due to a nrd auto-recalibration, and thereafter the signal rapidly returned to normal (positive excursion). as an example of the latter, if a foreign object or a finger contacts a key for period longer than the negative recal delay (nrd), the key is by recalibrated to a new lower reference level. then, when the condition causing the negative swing ceases to exist (e.g. the object is removed) the signal suddenly swings positive to its normal reference. it is almost always desirable in these cases to cause the key to recalibrate quickly so as to restore normal touch operation. the time required to do this is governed by prd. in order for this to work, the signal must rise through the positive threshold level pthr continuously for the prd period. l q 19 qt60248-as r4.02/0405
after the prd interval has expired and the auto- recalibration has taken place, the affected key will once again function normally. prd is fixed at 1 second for all keys, and cannot be altered. 5.7 burst length - bl the signal gain for each key is controlled by circuit parameters as well as the burst length. the burst length is simply the number of times the charge-transfer (?qt?) process is performed on a given key. each qt process is simply the pulsing of an x line once, with a corresponding y line enabled to capture the resulting charge passed through the key?s capacitance cx. qt60xx8 devices use a fixed number of qt cycles which are executed in burst mode. there can be up to 64 qt cycles in a burst, in accordance with the list of permitted values shown in table 5.3. increasing burst length directly affects key sensitivity. this occurs because the accumulation of charge in the charge integrator is directly linked to the burst length. the burst length of each key can be set individually, allowing for direct digital control over the signal gains of each key individually. apparent touch sensitivity is also controlled by the negative threshold level (nthr). burst length and nthr interact; normally burst lengths should be kept as short as possible to limit rf emissions, but nthr should be kept above 6 to reduce false detections due to external noise. the detection integrator mechanism also helps to prevent false detections. bl typical values: 2, 3 (48, 64 pulses / burst) bl default value: 2 (48 pulses / burst) bl possible values: 16, 32, 48, 64 5.8 adjacent key suppression - aks these devices incorporate adjacent key suppression (?aks? - patent pending) that can be selected on a per-key basis. aks permits the suppression of multiple key presses based on relative signal strength. this feature assists in solving the problem of surface moisture which can bridge a key touch to an adjacent key, causing multiple key presses. this feature is also useful for panels with tightly spaced keys, where a fingertip might inadvertently activate an adjacent key. aks works for keys that are aks-enabled anywhere in the matrix and is not restricted to physically adjacent keys; the device has no knowledge of which keys are actually physically adjacent. when enabled for a key, adjacent key suppression causes detections on that key to be suppressed if any other aks-enabled key in the panel has a more negative signal deviation from its reference. this feature does not account for varying key gains (burst length) but ignores the actual negative detection threshold setting for the key. if aks-enabled keys in a panel have different sizes, it may be necessary to reduce the gains of larger keys relative to smaller ones to equalize the effects of aks. the signal threshold of the larger keys can be altered to compensate for this without causing problems with key suppression. adjacent key suppression works to augment the natural moisture suppression of narrow gated transfer switches creating a more robust sensing method. aks default value: 0 (off) 5.9 oscilloscope sync - ssync pin 11 (s_sync) can output a positive pulse oscilloscope sync that brackets the burst of a selected key. more than one burst can output a sync pulse as determined by the setups parameter ssync for each key. the ssync function does not become effective until the part has been reset, or the desired key(s) are recalibrated. this feature is invaluable for diagnostics; without it, observing signals clearly on an oscilloscope for a particular burst is very difficult. this function is supported in quantum?s qmbtn pc software. ssync default value: 0 (off) 5.10 mains sync - msync the msync feature uses the sync pin. external fields can cause interference leading to false detections or sensitivity shifts. most fields come from ac power sources. rfi noise sources are heavily suppressed by the low impedance nature of the qt circuitry itself. noise such as from 50hz or 60hz fields becomes a problem if it is uncorrelated with acquisition signal sampling; uncorrelated noise can cause aliasing effects in the key signals. to suppress this problem the sync input allows bursts to synchronize to the noise source. the noise sync operating mode is set by parameter msync in setups. the sync occurs only at the burst for the lowest numbered enabled key in the matrix; the device waits for the sync signal for up to 100ms after the end of a preceding full matrix scan, then when a negative sync edge is received, the matrix is scanned in its entirety again. the sync signal drive should be a buffered logic signal, but never a raw ac signal from the mains; slow or erratic edges on msync can cause the device to sync on the wrong edge, or both edges. the device should only sync to the falling edge. since noise sync is highly effective and inexpensive to implement, it is strongly advised to take advantage of it anywhere there is a possibility of encountering low frequency (i.e. 50/60hz) electric fields. quantum?s qmbtn software can show such noise effects on signals, and will hence assist in determining the need to make use of this feature. if the sync feature is enabled but no sync signal exists, the sensor will continue to operate but with a delay of 100ms from the end of one scan to the start of the next, and hence will have a slow response time. a failed sync signal (one exceeding a 100ms period) will cause an error flag (see commands 0x05, 0x06). msync default value: 0 (off ) msync possible range: 0, 1 (off, on) 5.11 burst spacing - bs the interval of time from the start of one burst to the start of the next is known as the burst spacing . this is an alterable parameter which affects all keys. the burst spacing can be viewed as a scheduled timeslot in which a burst occurs. this approach results in an orderly and predictable sequencing of key scanning with predictable response times. l q 20 qt60248-as r4.02/0405
shorter spacings result in a faster response time to touch; longer spacings permit higher burst lengths and longer conversion times but slow down response time. bs default value: 1 (500s) bs possible range: 1..11 (500s .. 3ms) 5.12 lower signal limit - lsl this setup determines the lowest acceptable value of signal level for all keys. if any key?s reference level falls below this value, the device declares an error condition in the status bits. testing is required to ensure that there are adequate margins in this determination. key size, shape, panel material, and burst length all factor into the detected signal levels. this parameter occupies 2 bytes of the setups table. the low order byte should be sent first. lsl default value: 100 lsl possible range: 0..2047 5.13 host crc - hcrc the setups block terminates with a 8-bit crc, hcrc, of the entire block. the formulae for calculating this crc is shown in section 7. l q 21 qt60248-as r4.02/0405
table 5.1 setups block setups data is sent from the host to the qt in a block of hex data. the block can only be loaded in setups mode following two s e quential 0x01 commands (page 12). all devices this datasheet pertain to have the same block length. refer also to table 5.3, page 23 for further details, and all of section 5. 101 block length 21 - - 8 0..255 1 hcrc host crc byte 100 8 21 lower limit of acceptable signal; below this value, device declares an error. the low order byte should be sent first. 100 24 16 0..2048 2 lsl lower signal limit 98 7 20 lower nibble = burst spacing 1 24 4 bs = 0..11 1 bs burst spacing 97 6 20 bit 6 = mains sync, negative edge, 1 = enabled; default = 0 (off) 0 24 1 msync = 0, 1 1 msync mains sync 96 5 20 20 20 bits 5, 4: = bl, via lut, default = 48 (setting =2) bit 6 = aks, 1 - enabled bit 7 = scope sync, 1 = enabled 2 0 0 1 1 1 2 1 1 bl = 0, 1, 2, 3 aks = 0, 1 ssync = 0, 1 24 bl aks ssync burst length aks scope sync 72 4 19 range is in 0.5 sec increments; 0 = infinite; default = 10s (operand = 20) range is { infinite, 0.5...127s }; 255 is illegal to use 20 1 8 0..254 24 nrd neg recal delay 48 3 19 lower nibble = normal di limit, values same as operand (0 = disables key) upper nibble = fast di limit, values same as operand (0 does not work) 2 5 1 1 4 4 ndil = 0..15 fdil = 0..15 24 ndil fdil normal di limit fast di limit 24 2 18 18 lower nibble = neg threshold - take operand and add 4 to get value upper nibble = neg drift comp - via lut 6 10 1 1 4 4 nthr = 0..15 ndrift = 0..15 24 nthr ndrift neg thresh neg drift comp 0 1 page description default value key scope bits valid range bytes symbol parameter byte item # crc note: a crc calculator for windows is available free of charge from quantum research on request. table 5.2 key mapping some commands return bitfields related to keys. for example, command 0x07 (report all keys) returns 3 bytes containing flag bit s, one per key, to indicate which keys are reporting touches. the following table shows the byte and bit order of the keys. the table contains the key number reported in each bit. the key number is related to the x and y scan lines which address each particular key. each byte in the return stream represent s one set of keys along a y line, ie up to 8 keys. thus, key 0 is at location x0,y0 and key 19 is at location x3,y2. . note: byte 0 is returned first. l q 22 qt60248-as r4.02/0405 16 17 18 19 20 21 22 23 2 8 9 10 11 12 13 14 15 1 0 1 2 3 4 5 6 7 0 byte (y line) 0 1 2 3 4 5 6 7 bit (x line)
table 5.3 setups block summary typical values: for most touch applicatio ns, use the values shown in the outlined cells. bold text items indicate default settings. the number to send to the qt is the number in the leftmost column (0..15), not numbers from within the table. the qt uses lookup tables to translate the 0..15 to the paramet ers for each function. nrd is an exception: it can range from 0..254 which is translated from 1= 0.5s to 254= 127s with zero = infinity. 15 15 10 19 15 14 14 7.5 18 14 13 13 6 17 13 12 12 4.5 16 12 3,000s 11 11 3.3 15 11 2,750s 10 10 - 2.5 - 14 10 2,500s 9 9 2 13 9 2,250s 8 8 1.5 12 8 2,000s 7 7 1.2 11 7 1,750s 6 6 1 - 10 - 6 1,500s - 5 - 5 0.8 9 5 1,250s 4 4 0.6 8 4 1,000s 64 3 3 0.4 7 3 750s - 48 - default= 10s 2 - 2 - 0.3 6 2 - 500s - on on on 32 0.5 .. 127s 1 1 0.2 5 1 unused - off - - off - - off - 16 0 (infinite) unused key off 0.1 4 0 global global per key per key per key per key per key per key per key per key bs msync scope sync aks bl pulses nrd secs fdil counts ndil counts ndrift secs nthr counts parameter index number l q 23 qt60248-as r4.02/0405
6 specifications 6.1 absolute maximum electrical specifications operating temp .................................................................... -40 o c to +105 o c storage temp ......................................................................-55 o c to +125 o c v dd .................................................................................. -0.5 to +5.5v max continuous pin current, any control or drive pin ............................................. 10ma short circuit duration to ground, any pin ........................................................ infinite short circuit duration to v dd , any pin ........................................................... infinite voltage forced onto any pin .................................................. -0.6v to (vdd + 0.6) volts eeprom setups maximum writes .................................................. 100,000 write cycles 6.2 recommended operating conditions v dd ................................................................................ + 3.0v to 5.25v supply ripple+noise ................................................................... 5mv p-p max cx transverse load capacitance per key ..................................................... 0 to 20pf 6.3 dc specifications vdd = 5.0v, cs = 4.7nf, rs = 470k; ta = recommended range, unless otherwise noted k ? 80 30 internal /rst pullup resistor rrst drdy, /ss pins k ? 50 20 internal pullup resistors rp bits 11 9 acquisition resolution ar a 1 input leakage current iil 1ma source v vdd-0.7 high output voltage voh 4ma sink v 0.6 low output voltage vol v 2.2 high input logic level vhl v 0.8 low input logic level vil v 2.9 2.7 vdd internal reset voltage vr excluding external components ma 25 supply current, running iddr notes units max typ min description parameter 6.4 timing specifications max guaranteed is a min of 1.5mhz mhz 1.5 spi clock rate fck spi parameter controlled by host ns 667 clk period s9 spi parameter controlled by host ns 333 clk high pulse width s8 spi parameter controlled by host ns 333 clk low pulse width s7 spi parameter controlled by qt s 1 drdy low pulse width s6 spi parameter controlled by qt s 40 ? /ss to falling drdy s5 spi parameter controlled by qt ns 20 ? /ss to 3-state miso s4 spi parameter controlled by host ns 25 last ? clk to ? /ss s3 spi parameter controlled by qt ns 20 clk to valid miso s2 spi parameter controlled by host ns 333 /ss to first clk edge s1 % 8 burst modulation, percent fm khz 226 burst center frequency fc adjustable parameter via setups s 3,000 500 burst spacing t bs notes units max typ min description parameter l q 24 qt60248-as r4.02/0405
6.5 mechanical dimensions 6.6 marking l q 25 qt60248-as r4.02/0405 1 2 3 4 8 7 6 5 11 10 9 32 31 30 28 23 24 25 26 27 29 12 14 16 18 22 20 15 17 19 21 13 symbol a e e h h l p a millimeters inches min max notes min max notes e h h a e p a l o 9.25 8.75 0.344 0.354 0.09 0.20 0.003 0.008 0.45 0.05 0.75 0.15 1.20 0.018 0.002 0.030 0.006 0.047 0.80 0.30 bsc 0.80 0.45 0.031 0.012 bsc 0.031 0.018 6.90 7.10 0.272 0.280 - - o07 07 sq sq sq sq package type: 32 pin tqfp yes qt60248-ag 24 qt60248-asg -40 0 c to +105 0 c yes QT60168-AG 16 qt60168-asg -40 0 c to +105 0 c lead-free marking keys tqfp part number t a
7 appendix 7.1 8-bit crc algorithm // 8 bits crc calculation. initial value is 0. // polynomial = x 8 + x 5 + x 4 + 1 // data is an 8 bit number; crc is a 8 bit number unsigned char eight_bit_crc(unsigned char crc, unsigned char data) { unsigned char index; // shift counter unsigned char fb; index = 8; // initialise the shift counter do { fb = (crc ^ data) & 0x01; data >>= 1; crc >>= 1; if(fb) { crc ^= 0x8c; } } while(--index); return crc; } a crc calculator for windows is available free of charge from quantum research. l q 26 qt60248-as r4.02/0405
7.2 1-sided key layout this key design can be made on a 1-sided smt pcb. a single 0-ohm jumper allows the wiring to be done on a single side with full pass-through of x and y traces to allow matrix connections to be made across a large number of keys. key size, shape, and number of interleavings can be varied substantially from this drawing. the below drawing shows 6 interleave white spaces; only a double interleave is required in the case of smaller keys. the pcb is bonded to a panel on its underside, and the fields fire through the pcb, adhesive, and panel in that sequence. this results in a very low cost design. 7.3 pcb layout shown is an example pcb layout using inexpensive 1-sided cem-1 or fr-1 pcb laminate. the key layouts follow the design rules shown above. (pcb design shown uses a qt60326 chip but still represents a good example). l q 27 qt60248-as r4.02/0405 x y x y 0-ohm smt jumper
l q copyright ? 2004 qrg ltd. all rights reserved patented and patents pending corporate headquarters 1 mitchell point ensign way, hamble so31 4rf great britain tel: +44 (0)23 8056 5600 fax: +44 (0)23 8045 3939 www.qprox.com north america 651 holiday drive bldg. 5 / 300 pittsburgh, pa 15220 usa tel: 412-391-7367 fax: 412-291-1015 this device covered under one or more of the following united states and international patents: 5,730,165, 6,288,707, 6,377,009 , 6,452,514, 6,457,355, 6,466,036, 6,535,200. numerous further patents are pending which may apply to this device or the applications thereo f. the specifications set out in this document are subject to change without notice. all products sold and services supplied by qr g are subject to our terms and conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order acknowledgement. qprox, qtouch, qmatrix, qlevel, qslide, and qwheel are trademarks of qrg. qrg products are not suitable for medical (including lifesaving equipment), safety or mission critical applications or other similar purposes. except as expressl y set out in qrg's terms and conditions, no licenses to patents or other intellectual property of qrg (express or implied) are granted by qr g in connection with the sale of qrg products or provision of qrg services. qrg will not be liable for customer product design and c ustomers are entirely responsible for their products and applications which incorporate qrg's products. development team: dr. tim ingersoll, samuel brunet, hal philipp

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